An example illustrating data transmission between high-speed components within a single semiconductor device, or between two devices in a communication system, is represented by the system 10 shown in FIG. 1. In FIG. 1, transmitter circuitry 12 within device 8 (e.g., a microprocessor) sends data over one or more communication channels 14 (e.g., conductive traces “on-chip” in a semiconductor device or on a printed circuit board) to receiver circuitry 16 within device 9 (e.g., another microprocessor or memory). As a group, such communication channels 14 are often referred to as a “data bus,” which allows a group of data signals (e.g. a byte) to be transmitted from one device to another. Communication channels 14 are often two-way channels, and as such devices 8 and 9 would have both transmitter 12 and receiver 16 circuitry coupled to the channels 14; however this is not shown for convenience.
As discussed in U.S. Pat. No. 7,501,963 (“the '963 patent”), a data bus is susceptible to cross talk, simultaneous switching noise, intersymbol interference, and draws power based on the state of the data and/or frequency of data transition. One way to reduce these adverse effects and to prevent unnecessary power consumption is to encode the data. One specific form of data encoding that can be used is Data Bus Inversion (DBI).
Implementation of DBI includes encoding circuitry 13 in the transmitting device 8, which assesses the data bits (D1-Dn) (e.g., a byte) to be transmitted across the data bus and then decides, based on a particular DBI algorithm, if it would be advantageous to invert some or all of the data bits prior to transmission. If the data bits are inverted, an additional encoding indicator, referred to as a DBI bit, is also set at the DBI encoder 13 to indicate which data bits are inverted. Typically, as shown in FIG. 1, an extra channel 17 is needed so that the DBI bit may be transmitted in parallel with the data bits to inform receiving device 9 which groups of data bits have been inverted. Specifically, the DBI decoder 15 uses the DBI bit to return the incoming group of data bits (X1-Xn) to their original state (D1-Dn). Often, such decoding simply involves exclusive ORing the received data X1-Xn with the DBI bit.
Although not illustrated, another DBI approach involves calculating the DBI bit for each byte, but rather than sending the DBI bit in parallel with the byte over a DBI channel 17, sending a group of accumulated DBI bits simultaneously (e.g., a DBI byte) over the data channels 14 used for signaling. Such DBI byte can be sent either at the front or back end of the associated data signals. Using this DBI approach does not expand the pin count because a dedicated DBI channel 17 is not needed.
As pointed out in the '963 patent, there are several DBI algorithms known in the art. One DBI algorithm is referred to as the “minimum transitions” algorithm. While there may be variations of this technique, in general the minimum transitions algorithm begins by computing how many bits will transition during an upcoming cycle. When more than a certain number of transitions are predicted, the DBI encoder 13 inverts the data bits (D1-Dn), sets the DBI bit to a specified state (high or low depending on the implementation), and drives the inverted data bits and the DBI bit in parallel across the channels 14 and 17, with the DBI bit used to decode (i.e., de-invert) the inverted data bits at the DBI decoder 15 prior to use in the receiving device 9.
Two other well-known DBI algorithms include the “minimum zeros” algorithm and the “minimum ones” algorithm. The purpose of these algorithms is, respectively, to minimize the number of binary zeros or binary ones transmitted across the channel 14. Such algorithms conserve power when the transmitter or receiver circuits coupled to the communication channels are referenced to a particular power supply voltage through a resistor, and therefore will draw more power when transmitting or receiving a particular data state. For example, if a pull-up resistor connected to the high power supply voltage (Vddq) is used in a particular transmitter or receiver circuit, driving a logic ‘0’ will require more power than would driving a logic ‘1’. In this instance, use of a minimum zeros DBI algorithm would be indicated to try and transmit as many logic ‘1’ states across the transmission channels 14 as possible. Likewise, if a pull-down resistor connected to the low power supply voltage (Vssq) is used, a minimum ones algorithm would be indicated.
As communication systems grow more complicated, and become more configurable, it is becoming more complicated to pick a particular DBI algorithm that will be useful in all circumstances. For example, a manufacturer of device 8 may not necessarily know the type of device 9 that a particular system integrator might wish to couple to device 8. Or, device 9 may be variable in manners affecting the communication channels 14, in particular in the manner in which such channels are terminated. It is therefore difficult for the manufacturer of device 8 to provide a one-size-fits-all DBI solution. In fact, any particular data encoding algorithm chosen by the manufacture for device 8 could be counter-indicated by the particulars of device 9.
This disclosure presents a solution to such problems, and provides for devices with programmable DBI encoding algorithms dependent on the termination scheme used with a receiving device in the system.